Job Description

Analog Design & Layout Engineer

Direct Hire

Location- 1001 Marina Del Rey California 90292

About the Role

We are seeking a highly motivated and skilled engineer to join the Prototype Integration and Engineering Services (PIES) team, a critical unit within MOSIS 2.0 . This role plays a pivotal part in enabling access to university nanofabs and industry prototyping/production fabs, directly supporting Government- and Industry-funded R&D projects . The applications range from advanced RF-spectrum communications and sensing (e.g., 5G/6G) to cutting-edge digital design .

This is an ideal opportunity for an engineer who enjoys hands-on design work while also contributing to academic initiatives and collaborative research. You’ll work directly with MOSIS 2.0 customers and USC teams to design, layout, and support circuit implementation across a broad range of semiconductor process technologies.

Key Responsibilities

Customer and Project Support

• Collaborate with MOSIS 2.0 customers to deliver high-quality analog or digital circuit designs.
• Provide layout implementation support and technical guidance on schematic capture, simulation, layout creation, and design rule compliance across technologies such as CMOS, BiCMOS, and III-V.

Academic and Research Engagement

• Assist with USC’s tape-out classes by demonstrating layout best practices and troubleshooting issues.
• Contribute to USC ECE-funded research projects through design/layout support, post-layout simulation, parasitic extraction, and verification.

Technical Documentation & Collaboration

• Prepare detailed design documentation, layout closure reports, and technical presentations.
• Collaborate with USC faculty, students, and industry stakeholders to improve design methodologies and workflow efficiencies.

Qualifications

Education:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Electronics, or a related field.

Technical Skills:

• At least 3 years of experience in analog circuit design, RF design, digital circuit design, or physical layout.
• Proficiency with CAD tools such as Cadence Virtuoso , SPICE simulators , Mentor Graphics , or equivalent.
• Solid understanding of DRC, LVS , parasitic extraction, and layout verification.
• Experience with electromagnetic, photonic, or device-level simulations is a plus.

Soft Skills:

• Strong interpersonal and communication skills with a customer-focused approach.
• Experience in teaching, tutoring, or conducting workshops is highly desirable.
• Ability to adapt to various process technologies and evolving project requirements.

Why Join Us?

This role offers a unique chance to work at the intersection of cutting-edge semiconductor R&D , academic excellence , and industry collaboration . You’ll help bridge the gap between innovation and production while working within a highly supportive and pioneering engineering environment.

Apply now to be part of the next wave of microelectronics innovation with USC and MOSIS 2.0.

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